High speed SRAM is usually designed so that it is synchronized in its operation. That is, its read write operations are triggered and controlled by clock timing. The local clock generator for the SRAM array is, therefore, a critical part in the SRAM design. High performance SRAM requires an ability to adjust certain timing functions in place in order to allow early mode/late mode timing adjustments, and to adjust internal timing adjustments, which allow high performance with minimum timing margins. In the prior art, such timing adjustments have been implement via fuse links or EPROM.